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Photonic curing is a large‐area, high‐throughput thermal processing technique that uses high‐intensity pulsed light to selectively cure thin films on thermally sensitive substrates. This study employs 3‐dimensional (3D) simulation to show, for the first time, that gate geometry significantly impacts peak curing temperature during photonic curing. The simulation results are experimentally validated by photonically curing solution‐processed indium zinc oxide for thin‐film transistors with different bottom gate geometries and comparing their performance to thermally annealed control devices. Under the same photonic curing pulse, for a fixed aspect ratio, peak photonic curing temperature increases with larger gate area, while for a fixed area, peak photonic curing temperature decreases with increasing aspect ratio. For different gate areas and aspect ratios, the simulated peak photonic curing temperature varies from ≈200 to 450 °C, which strongly impacts metal‐hydroxide to metal‐oxide conversion in sol–gels. Thus, the subsequent transistor performance is strongly influenced by the gate geometry. For example, for increasing gate area with fixed aspect ratio of 1, the average mobility increases from 1.61 to 12.52 cm² V⁻¹s⁻¹, while the threshold voltage decreases from 2.14 to −5.68 V. Thus, this study provides valuable insights for adopting 3D simulation to design transistors for complex large‐area electronics using photonic curing. 

Abstract Fabricating flexible electronics on plastic is often limited by the poor dimensional stability of polymer substrates. To mitigate, glass carriers are used during fabrication, but removing the plastic substrate from a carrier without damaging the electronics remains challenging. Here we utilize a large-area, high-throughput photonic lift-off (PLO) process to rapidly separate polymer films from rigid carriers. PLO uses a 150 µs pulse of broadband light from flashlamps to lift-off functional thin films from glass carrier substrates coated with a light absorber layer (LAL). Modeling indicates that the polymer/LAL interface reaches above 800 °C during PLO, but the top surface of the PI remains below 120 °C. An array of indium zinc oxide (IZO) thin-film transistors (TFTs) was fabricated on a polyimide substrate and photonically lifted off from the glass carrier. The TFT mobility was unchanged by PLO. The flexible TFTs were mechanically robust, with no reduction in mobility while flexed. 

Abstract In metal‐oxide thin‐film transistors (TFTs), high‐kgate dielectrics often yield a higher electron mobility than SiO₂. However, investigations regarding the mechanism of this high‐k“mobility boost” are relatively scarce. To explore this phenomenon, solution‐processed In₂O₃TFTs are fabricated using eight different gate dielectrics (SiO₂, Al₂O₃, ZrO₂, HfO₂, and bilayer SiO₂/high‐kstructures). With these structures, the total gate capacitance can be varied independently from the semiconductor–dielectric interface to study this mobility enhancement. It is shown that the mobility enhancement is a combination of the effects of areal gate capacitance and interface quality for disordered oxide semiconductor devices. The ZrO₂‐gated TFTs achieve the highest mobility by inducing more accumulation charge with higher gate capacitance. Surprisingly, however, when the gate capacitance is held constant, no mobility enhancement is observed with the high‐kgate dielectrics compared to SiO₂.